The present invention relates to digital apparatus for performing a binary multiplication operation. In particular, the present invention teaches a method and apparatus for improving the multiplication throughput within the arithmetic section of a digital computer. The method essentially consists of performing a one's complement multiplication of a multiplicand by successive eight bit bytes of the multiplier, positioning the successive partial products and carries and adding the final partial product to a converted final partial carry to produce the final product in a two's complement format.
The primary advantage of the present invention being an improved throughput in a computer's arithmetic section. Specifically, the present invention is able to perform an eight bit multiplication cycle in fifty nanoseconds. Whereas, using apparatus such as a Sperry Univac.RTM. Series 1100/80 computer, it would take approximately one hundred nanoseconds to multiply the same multiplicand by only four multiplier bits. Therefore, a four-to-one improvement is achieved via the use of the present method and apparatus.
Previously too, the multiply operation was performed with SSI/MSI integrated circuits in a two's complement operation, that albeit produced the same result, but which circuitry was too slow for most scientific applications. It is therefore a primary object of the present invention to minimize the amount of time required to perform a multiplication operation.
It is a further object of the present invention to use gate arrays instead of SSI/MSI integrated circuitry to perform the multiplication operation. These objects and others are thus served via the present method and apparatus as described and claimed hereinafter.